In general, non-volatile memory devices are solid state memory devices having memory cells that can retain stored data without electrical power or otherwise having to be periodically refreshed. There are various types of non-volatile memory including, for example, ROM (read only memory), PROM (programmable read-only memory), EPROM (erasable programmable read-only memory), EEPROM (electrically erasable programmable read-only memory) and Flash memory (also referred to as Flash EEPROM). Among the various types of non-volatile memory, flash memory technologies offer high density, low cost, high-speed data read, and electrically reprogrammable nonvolatile memory solutions, which are commonly used in various applications such as embedded applications. Flash EEPROM memory devices can be designed having NOR type or NAND type flash memory cell frameworks, as is known in the art. As compared to NOR type flash memories, NAND type flash memory provides a level of integration and a memory capacity similar to that of dynamic RAM, and is thus commonly used.
FIG. 1 is a schematic block diagram of a flash memory device (10) having a conventional architecture. In general, the flash memory device (10) includes high-voltage generator circuits (100), row decoder and control circuits (110) (or X-decoder), a memory cell array (140), a page butter (150), a column decoder (or Y-decoder) and I/O buffer (160) and a program controller (170). The voltage generator circuits (100) comprises a high voltage (Vpp) generator (101), a selection voltage (Va) generator (102), a program voltage (Vpgm) generator (103), a pass voltage (Vpass) generator (104), and a read voltage (Vread) generator (105), for generating various voltages that are used to operate the flash memory during program, read, erase operations, etc., as discussed below.
The memory array (140) comprises a plurality of transistors arranged in a matrix of rows and columns and having memory cells that are partitioned into a plurality of n memory blocks MB1˜MBn (generally, MBi). The memory array (140) includes a set of row control lines that are applied to each memory block MBi. For instance, as shown in FIG. 1, row control lines input to the memory block MB1 include a string select line SSL, ground select line GSL and wordlines WL0˜WL31. The row control circuit block (110) selectively activates the row control lines SSL, WL0˜WL31 and GSL by applying driving voltages that are used in memory programming operations, erase operations or read operations.
A plurality of bit lines BL1˜BLm (generally, BLi) are arranged in parallel and extend through all memory blocks MB1˜MBn of the array (140). Each bit line BL1˜BLm is operatively connected to the page buffer (150) and column decoder and I/O buffer blocks (160), which implement known functions and circuitry for reading data stored in the memory cells, for determining the states of memory cells during programming operations, for controlling potential levels of the bit lines BLi for various operating modes, and for storing data to be stored to, or read from, the memory cells. The program controller (170) generates control signal to control the functions of the column control and I/O buffer circuitry (150, 160), the row control circuitry (110) and the high-voltage generator circuits (100).
The memory array (140) depicted in FIG. 1 has a NAND type flash EEPROM memory framework, in which each memory block MBi includes a plurality of strings (or, “NAND strings”) of serially connected floating gate EEPROM transistors, which are connected to corresponding ones of the bit lines BL1˜BLm in each memory blocks MB1˜MBn. For illustrative purposes, only one memory cell block, MB1, is illustrated in detail in FIG. 1 having a plurality of NAND strings of 32 EEPROM cell transistors M0˜M31 connected in series between a source of a string select transistor SST (first select transistor) and a drain of a ground select transistor GST (second select transistor). Although FIG. 1 depicts an embodiment where each NAND cell unit is formed of 32 EEPROM floating gate transistors, NAND cells can be formed with 8 or 16 memory cells, for example.
For each NAND string, the drain of the SST is connected to a corresponding bit line BLi and the source of the GST is connected to the common source line CSL. In this regard, each NAND string is connected between a corresponding bit line BLi and reference potential provided on the CSL. The selection line SSL is commonly connected to the gate terminals of each SST in the same row of the memory block MB1, the selection line GSL is commonly connected to the gate terminals of each GST in the memory block MB1. The control gates of the EEPROM memory cell transistors M0˜M31 in each NAND string are commonly connected to respective word lines WL0˜WL31.
The row control circuit block (110) generally operates by decoding received address signals and selectively activating the string select line SSL, wordlines WL0˜WL31 and the ground select line GSL with driving voltages that are needed in a program operation, an erase operation or a read operation. The row control circuit block (110) comprises a block decoder/driver circuit (115), a line driver block (120), and a pass gate block (130).
The line driver block (120) comprises a plurality of drivers including a string select (SS) driver (121), a word line select (Si) driver (122) and a ground select (GS) driver (123), which generate driving voltages that are output on respective selection signal lines SS, SO˜S31, and GS. The selection signal lines SS, S0˜S31 and SGS are activated to the required voltages by the corresponding selection circuits (or driving circuits) based on row address decoding information PA. The string select driver (121) generates and outputs string select driving signals on the SS selection line, the Si driver (122) generates and outputs wordline driving signals on selection lines S0˜S31, and the GS driver (123) generates and outputs ground select driving signals on the GS selection line GS.
The pass gate block (130) includes high-voltage pass transistors PGS, P0˜P31 and PSS (or generally, Pi). The ground selection line GSL, wordlines WL0˜WL31, and string selection line SSL are respectively connected to the GS, S0˜S31 and SS selection signal lines through respective pass transistors PGS, P0˜P31 and PSS in the pass gate block (130). The gate terminals of the pass transistors Pi in the pass gate block (130) are commonly connected to a block wordline that is connected to the output of the block selection decoder/driver unit (115). The block selection unit (115) selectively generates a control signal BLKWL in response to a decoded address signal BA (block address) to drive the pass gate transistors Pi. The block selection unit (115) generates the block wordline control signal BLKWL using the VPP voltage signal generated and output from the high voltage generator (101).
The operation of a NAND type flash EEPROM memory as depicted in FIG. 1 will now be described in further detail with reference to FIGS. 7˜10. FIG. 7 illustrates an EEPROM memory cell (60) having a control gate (61) and floating gate (62) stacked above a channel region (63) between drain/source diffusion regions (64) in the active region of a semiconductor layer (65). The control gate (61) is coupled to a wordline of the memory array. As is well understood in the art, the EEPROM memory cell (60) can be programmed using a Nordheim-Fowler cold tunneling process, wherein the floating gate (62) is programmed to store an amount of electric charge that corresponds to the data stored in the cell (60). In an erasing operation, control voltages are applied so that electrons are removed from the floating gate (62) to the channel region (63) and in a programming operation, electrons are injected into the floating gate (62) from the channel region (63) by Fowler-Nordheim (F-N) tunneling.
Depending on the application, the EEPROM memory cells can be operated with various storage level ranges per cell. In Single Level Cell (SLC) technology, each EEPROM memory cell can store 1 bit of data using two voltage levels, whereas in Multi-Level Cell (MLC) technology, each EEPROM memory cell can store 2 bits of data per cell, using four voltage levels. FIG. 8 is an exemplary illustration of threshold voltage distributions for a plurality of EEPROM floating gate transistors forming an array EEPROM memory cells wherein each EEPROM memory cell is programmed in a binary mode to have one or two programming states. The curve 71 represents a distribution of threshold levels of those EEPROM memory cells within a memory array that are in an erased state (“1” data state), wherein the threshold voltage levels range from −1˜−3 volts. The curve 72 represents a distribution of the threshold levels of those memory cells within an array that are in a programmed state (“0” data state), wherein the threshold voltage levels range from 1˜3 volts. The voltages Vo and V1 represent the verify voltage levels for the different states that are determined during programming operations and R1 (e.g., OV) represents a read voltage that is used to read the state of the EEPROM memory cells in the binary mode.
A NAND type flash memory array such as the array (140) depicted in FIG. 1 typically performs a programming operation by erasing memory cell data block by block (sector by sector) and then programming the memory cells in the erased memory block in page units. A page may be defined to have a page size that is the same or smaller than the number of memory cells Mi commonly connected to the same wordline WLi in the memory array and accessed at the same time. For instance, in the memory cell array (140) of FIG. 1, the number m of bit lines (columns) may be 8,512, which are logically divided into interleaved even and odd columns, such that a given wordline WLI is partitioned into an odd and even page, each containing 4,256 memory cells (or 532 bytes). Since each block MBi contains 32 wordlines, each block MBi can be considered as having 64 pages, partitioned into two sub blocks of 32 pages, where each sub-block can be considered a block unit for an erase operation.
The data stored in each memory block MBi can be simultaneously erased prior to programming. A block erase process can be performed by raising the bulk substrate voltage to an erase voltage Verase of, for example, 20V and grounding the word lines of the selected unit block while placing the bit lines (BL), select lines SSL, GSL and common source line CSL of the unit block in a floating state. In a binary programming mode, the memory cells are programmed into an “erased” state having voltage thresholds that may vary in the range of −1v to −3v, as depicted in FIG. 8. Following a block erase operation, the memory cells within the unit block can be programmed on a unit page basis, as discussed below with reference to FIGS. 9 and 10.
FIGS. 9 and 10 schematically illustrate a programming operation of a NAND type flash memory device according to a conventional process. FIG. 9 schematically illustrates a unit block (90) of memory cells in the memory array (140) of FIG. 1, where it is assumed that the memory cells Mi of a selected wordline WLi for the unit block (90) represents a unit page that is selected for programming. FIG. 10 illustrates control voltages that are applied to selected and unselected wordlines in of the unit block (90) FIG. 9 to program memory cells Mi of the selected wordline Wi.
Referring to FIGS. 9 and 10, the memory cells are programmed during a program execution period by driving the applying a programming voltage Vpgm to the selected word line WLi with a programming voltage Vpgm and grounding the selected bit line(s) (i.e., bit lines connected to NAND cell units having EEMPROM cells Mi to be programmed from an erase state), while driving the unselected word lines with a pass voltage Vpass, for example 8˜10V, and charging the unselected bit lines to VDD, for example 3V. Moreover, the select signal line SSL is connected to VDD and the select signal line GSL is grounded (OV).
In one technique known as ISPP (incremental step pulse programming), the programming voltage Vpgm applied to the selected WLi is a pulsed signal that is incrementally applied to the selected wordline WLi and stepped up (e.g., step size of 0.5 V) from a initial voltage (e.g., 15V) to a higher level (e.g., 18˜20V) is sequential program execution periods. In periods between the Vpgm pluses, program verify operations are performed to read the programmed level of each cell being programmed to determine whether the programmed level is equal to or greater than the verify voltage level Vvfy associated with the target programming state.
More specifically, in a read and verify operation, the a read pass voltage Vread of 4.5V˜5V, for example, is applied to the selection lines SSL and GSL and the unselected word lines to make the transistors SST, GST and unselected memory cells operate as pass gates. Moreover, the selected word line WLi is driven by a voltage that is specified for a given read and verify operation to determine whether a threshold voltage of the given memory cell has reached a target voltage threshold level. The selected bit lines are precharged to a high level, for example 0.7 V. If the threshold voltage is higher than the read or verify level, the potential level of the selected bit line maintains the high level, whereas if the threshold voltage is lower than the read or verify level, the potential level of the selected bit line decreases to a lower level.
As depicted in FIG. 10, during a programming operation, the control voltages Vpgm and Vvfy are sequentially applied to the selected wordline WLi in respective program execution and verify read periods of a programming cycle. Moreover, the pass voltages Vpass and Vread are sequentially applied to the unselected wordlines in respective program execution and verify read periods of the programming cycle. In the conventional memory architecture of FIG. 1, the Vpass and Vread pass voltages are high voltages (greater that supply voltage VDD) that are both applied sequentially to the same unselected W/Ls during program or verify operations, but are generated by different voltage generators (104) and (105).